1. Field of the Invention
The present invention relates to a split polycilicon process in a CMOS image integrated circuit and more particularly a method of forming poly gate and polycide gate with an almost equal height fabricated on a substrate to reduce the sheet resistance of the poly gate electrode.
2. Description of the Prior Art
Integrating the periphery circuits on a chip is a stream of electronic products in the technology development of the electronic industry. Recently, the improvement of semiconductor processing make the integration of memory cells and periphery circuits on one chip possible.
Taking an image device as an example, in order to improve the performance and resolution of images, each image has to be divided into millioned pixels. Then each pixel is memorized in a memory cell by the form of digital data. One aspect to show the characteristics of an image device is the accuracy of electronic signals memorized by memory cells for each pixel array. If the problem of current leaking occurs in the memory cells, the electronic signals of pixels can not be recorded exactly which will produce many dots on the image. Another aspect to show the characteristics of an image device is the accessing speed of the periphery circuits integrated on the chip. The accessing speed has to be fast enough for dealing with a great amount of data. Therefore, for an image device a chip should correspond to two demands concurrently. One of the demands is that current leaking is rigidly limited, but the accessing speed is not important. Another demand is that a high accessing speed is necessary, but the current leaking is not the key consideration.
In a semiconductor device, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of the most important elements for the VLSI integrated circuits. A MOSFET includes a gate structure, a source and a drain, wherein the source and drain are located at the sides of the gate structure. The gate structure includes a metal layer at the top named gate electrode, an oxide layer under the metal layer named gate oxide, and a semiconductor layer at the bottom.
Typically, the metal layer at the top of the gate structure is formed by polysilicon, thereby the gate structure is named poly gate. Because polysilicon does not have a lowest resistance, sometimes a layer of silicide is deposited overlying the polysilicon layer to form a polycide gate for lowering the resistance.
Because poly gate does not have a lowest resistance, its accessing speed is not the fastest. But the problem of current leaking in poly gate is not serious, which makes poly gate be a good element for the pixel array area in a CMOS image device. On the other hand, the problem of current leaking in polycide gate is worse than that in poly gate, but polycide gate has a lower resistance which can decrease the TC time delay and increase the device switching speed. Therefore, the polycide gate is better than poly gate to be the element for the periphery circuit area in a CMOS image device for providing a high speed to deal with a great amount of pixel data in the periphery circuit area. As described above, fabricating a poly gate and a polycide gate on one substrate in a CMOS image integrated circuit is called "Split Polysilicon Process".
In order to form poly gate and polysice gate on one silicon substrate concurrently, several issues about the process and products are derived. Referring now to FIG. 1, a cross-sectional view of the poly gate and polycide gate formed on a substrate according to a prior art of the present invention, a gate oxide layer 2 is formed on a semiconductor substrate 1. Then, a poly gate including a polysilicon layer 3 is formed at the poly gate area by the methods of deposition, photolithography and etching. Next, a polycide gate is formed at the polycide gate area, wherein the polycide gate has a polysilicon layer 3 and a silicide layer 4.
Because polysilicon has a higher resistance than polycide, and the height of poly gate is lower than the height of polycide gate, as shown in FIG. 1, the conventional structure in FIG. 1 make the poly gate has a much higher sheet resistance than the polycide gate. Therefore, the accessing speed of the products produced by the conventional technology is not good enough. For the image device described above, the obvious difference of accessing speed between the cell area and the periphery area can not make the device achieve a best operating state. Therefore, the present invention seeks to provide a method for solving this problem.